Investigating opportunities for instruction-level parallelism for stack machine code

Today, many general-purpose register-file (GPRF) architectures implement instructionlevel-parallelism (ILP) techniques to improve performance. Less has been done in this area for the so-called ‘stack architecture’. Nonetheless, stack architectures have many advantages over GPRF architectures. Applying ILP techniques in the stack processor domain might ultimately achieve similar, or better, performance to that of register machines. This thesis investigates evidence for naturally occurring ILP in stack-code, and potential performance gains for ILP exploitation. Static analysis is a major area of methodology applied here. In particular this thesis: • Investigates, defines and measures parallelism in standard stack-code. • Investigates effects of certain existing stack-code optimisations. • Applies ILP techniques common to GPRF machines to stack-code, and investigates their effects, in particular loop unrolling, superblock formation, and branch prediction. • Utilises a synthetic approach to superblock formation to estimate ILP conditions under a branch-prediction mechanism. An ‘ideal stack machine’ with unlimited resources was assumed as a base model, then varied non-ideal models were then assumed, and ILP performance gains measured. For each model, varied instruction latencies were also assumed. The effects of architectural variations are thus examined. This thesis demonstrates that ILP exists in the stack code and can potentially improve the performance of appropriate stack machines. Loop unrolling is shown to be effective in enhancing ILP for stack code, and local variable optimisation is also shown to be of importance in partnership with this approach. Creation of superblocks (called “dynamic superblocks” or “artificial superblocks”) constructed through assumed 1-level branch prediction is also shown to be effective. Overall the thesis demonstrates that there is ample evidence of exploitable ILP in stack compiler generated code, and that stack machines could be developed which rank considerably higher in performance terms than the existing stack processor paradigm as it stands.